Project Lead: Dr. Sung Kyu Lim
Sponsoring Organization: DARPA
Project Synopsis: Critical next-generation defense systems, such as autonomous vehicles and arrays of sensors, will be deployed in distributed settings where resources for exporting newly encountered data might be scarce or unavailable. RTML seeks to solve this problem by creating no-human-in-the-loop hardware generators and compilers to enable the fully automated creation of ML Application-Specific Integrated Circuits (ASICs) from high-level source code. RTML will focus on building an end-to-end general purpose compiler that can transform a high-level ML framework into Verilog. This, in turn, may allow future engineers to rapidly develop and deploy large-scale real-time machine learning systems with customized hardware that can execute intensive ML algorithmic tasks on chip, without the need for external computational resources.